The use of fast hopping frequency synthesizers is well known in the art for applications such as Frequency Hopping Spread Spectrum (FHSS) or Multi Band Orthogonal Frequency Division Multiplexing Ultra Wide Band (MB-OFDM-UWB) transmitters and receivers. As is the case in all transceivers, the synthesized frequency source (i.e. the local oscillator (LO)) is used to both modulate the signal in the transmitter and to demodulate the signal in the receiver.
Local oscillator signals are normally generated using a phase locked loop (PLL) coupled to a crystal oscillator that provides the frequency reference. The loop bandwidth of the PLL determines its settling rate as well as some of the phase noise properties of the generated local oscillator signal. The underlying trade off is that lower loop bandwidths may provide lower phase noise by better rejecting the reference phase noise but at a cost of longer settling times.
FIG. 1 illustrates the basic frequency plan of the WiMedia Physical Layer Specification version 1.1, incorporated herein by reference in its entirety. In accordance with the specification, the usable frequency spectrum of 3 to 11 GHz, generally referenced 10, is divided into five band groups 18, labeled Band Group #1 to Band Group #5. Each band group is further divided into three bands. For example, Band Group #1 is divided into three bands: Band #1 12 centered around 3432 MHz, Band #2 14 centered around 3960 MHz and Band #3 16 centered around 4488 MHz. Each transmission band in all band groups has a bandwidth of 528 MHz.
FIG. 2 illustrates a typical time-frequency allocation for the WiMedia Physical Layer. Each OFDM symbol 32, having a duration of 242 ns, is transmitted followed by a zero padded suffix (ZPS) 34, having a duration of 80 ns, during which zeros are transmitted. The frequency synthesizer in the transmitter and receiver is expected to hop during the hopping duration within the last 9 ns portion 36 of the ZPS.
The OFDM symbols 32 and ZPS durations 34 are transmitted in the various frequency bands at different time intervals according to a pre-determined sequence referred to as a Time Frequency Code (TFC). With reference to FIG. 2, the example time frequency code shown is 1-2-3-1-2-3. The first symbol 20 and its ZPS 26 are transmitted in Band #1, the second symbol 22 and its respective ZPS 28 are transmitted in Band #2 and the third symbol 24 and its corresponding ZPS 30 are transmitted in Band #3. This sequence is repeated throughout the duration of the entire packet.
Note that in this prior art transmission scheme it is imperative that the synthesizer be capable of switching frequencies up to a 1056 MHz hop distance within 9 ns. It is appreciated by one skilled in the art that a single phase locked loop with reasonable phase noise and a settling time of 9 ns is impractical to construct using conventional means.
FIG. 3 illustrates a first prior art synthesizer architecture, generally referenced 40. A crystal 42, coupled to a crystal oscillator 44 generates a reference signal 46 onto which a plurality of phase locked loops (PLLs) are locked. The reference signal 46 frequency is effectively multiplied by the N PLL circuits 48 (i.e. by an integer or rational multiplier) yielding the necessary local oscillator signals simultaneously. The LO signals enter a switch circuit 50 which outputs the required local oscillator signal 52. The switch is operative to choose which signal to place on the local oscillator signal port 52. The switch selects one of the PLL signals in accordance with the hopping sequence 54 generated by the hopping sequence logic 56. The hop sequence is either pre-determined by a standard, negotiated between the receiver and transmitter or generated by a pseudo random sequence, the generating function of which is known a priori to the receiver and transmitter.
A major drawback of this architecture is that for each possible frequency there needs to be a PLL running continuously. This requires a large area (i.e. in either board size or die area) with a consequent large power dissipation. Further, a large enough frequency set may make this scheme impractical to construct.
FIG. 4 illustrates a second prior art synthesizer architecture, generally referenced 60. A crystal 62, coupled to a crystal oscillator 64 generates a reference signal 65 onto which a plurality of phase locked loops (PLLs) are locked. The reference signal 65 frequency is effectively multiplied by the N PLL circuits 66 (i.e. by an integer or rational multiplier) yielding some of the necessary signals and possible signals with frequency differences thereof. A configurable mixer stage 68 effectively mixes (i.e. multiples) some or all of the signals generated by the PLLs 66 to yield the required local oscillator signal 74. Configurable mixer stage 68 can be configured to mix a different set of PLL signals for the various local oscillator signal 74 frequencies required. In some cases mixer techniques such as Single Side Band (SSB) mixers or sub harmonic mixers are used to create the desired effect. The hopping sequence 71 is generated by hopping logic circuit 70. The sequence is either pre-determined by a standard, negotiated between the receiver and transmitter or generated by a pseudo random sequence, the generating function of which is known a priori to the receiver and transmitter.
Although this prior art architecture generally requires a smaller number of PLL circuits than the architecture shown in FIG. 3, the configurable mixer stage usually generates (aside from the desired LO tone) a number of spurious tones which degrade the Spectral Emission Mask (SEM) in the transmitter and pick up (i.e. demodulate into the same frequency band) undesired signals in the receiver.
A third prior art LO architecture, generally referenced 80, constructed in accordance with Mode #1 (i.e. Band Group #1) of the WiMedia 1.1 specification is shown in FIG. 5. A crystal 82, coupled to a crystal oscillator 84 generates a reference signal 104 with a frequency of 44 MHz. The signal is then input to two PLLs, namely PLL1 86 and PLL2 88. Both PLLs use a divide by 2 quadrature topology and generate in-phase (I) and quadrature (Q) LO signals with a 90 degree phase shift between them. PLL1 86 generates an I/Q LO signal pair 90 at a frequency of 3960 MHz. PLL2 88 generates a second I/Q LO signal pair 92 at a frequency of 528 MHz. Note that the frequency difference between the various frequencies in Band Group #1 is an integer multiple of 528 MHz. Therefore, PLL1 86 generates exactly the Band #2 LO, while PLL2 88 generates the frequency difference needed that is mixed with the signal generated by PLL 1 in order to obtain Band #1 and Band #3 LO signals.
The I/Q LO pair 92 is input to a frequency selector block 94 which functions to generate either a +528 MHz tone, a −528 MHz tone or a 0 MHz (DC) tone by inverting the Q signal or setting a DC voltage in both the I/Q pairs, respectively. The frequency selector mode of operation is determined by the hopping sequence 96 generated by the hopping logic 106. The resultant I/Q LO pair 98 enters a single sideband (SSB) mixer circuit 102 along with I/Q LO pair from PLL1 86. The SSB mixer generates the required I/Q LO signal pair 100 at frequencies of either (1) 3432 MHz when a −528 MHz LO is generated by frequency selector 94, (2) 3960 MHz when a DC signal is generated by frequency selector 94 or (3) 4488 MHz LO signal when a +528 MHz LO is generated by frequency selector 94. This architecture, therefore, is capable of generating all three LO signals for Band Group #1. Furthermore, since the frequency selector block operates in an open loop mode, its switching time can meet the required 9 ns period.
A major disadvantage of this architecture is that although the circuit reduces the number of PLL circuits required, with a reduction in area and power count, the SSB mixer 102, along with the desired LO signal, generates a frequency comb at frequencies of 3960 MHz±n528 MHz, where n is an integer. This results in both spurious emissions in neighboring UWB bands in the transmitter and reduced Adjacent Channel Interferer (ACI) performance in the receiver. Note that this UWB architecture follows the general frequency synthesizer architecture of FIG. 4.
A prior art receiver architecture compliant with the WiMedia 1.1 specification is shown in FIGS. 6A and 6B. This synthesizer architecture, generally referenced 110, is a special case of the architecture depicted in FIG. 3. A crystal 146, coupled to a crystal oscillator 148 generates a frequency reference signal 150. The reference signal is input simultaneously to three quadrature PLLs 152, 154, 156, which function to generate LO signals at the three desired frequencies, namely 3432 MHz, 3960 MHz and 4488 MHz, respectively. The I/Q signals for the three LOs 158, 160, 162, respectively represent a pair of 90 degree phase shifted signals for each LO.
The synthesizer architecture 110 is coupled to the receiver architecture, generally referenced 125. The RF signal is picked up by an antenna 112 and amplified by a low noise amplifier LNA 114. The amplified LNA signal 116 is simultaneously input to three down conversion circuits (i.e. quadrature mixers) 118, 120, 124. Each one of the three quadrature mixers is controlled by a respective activation signal which is operative to switch the circuit off, effectively generating a zero output. The three activation signals 166 are generated by the hopping logic 164. Each of the three I/Q mixer pairs 118, 120, 124 uses the corresponding I/Q LO pair 158, 160, 162, respectively. The resultant I/Q baseband signals 122, 123, 126, respectively, are summed separately for the in-band baseband signal (via summing circuit 136) and the quadrature baseband signal (via summing circuit 128). The I/Q baseband signals 138 and 139 are filtered by low pass filters 140 and 141, respectively, to yield the filtered I/Q baseband (BB) signals 142 and 143, respectively. These signals are then sampled and processed by the digital receiver (not shown).
Although this receiver architecture does not suffer from the spurious tone effects as does the architecture of FIG. 5, it does require three PLL circuits and three down conversion mixer pairs creating a significant size and power dissipation penalty.
Thus, there is a need for a fast hopping frequency synthesizer scheme that meets the requirements of the WiMedia specification. The scheme should be capable of providing the three required frequencies without generating excessive frequency spurs, should exhibit a quiet spectrum at LO frequencies, and should minimize both power consumption and silicon real estate.